This invention relates to a networked processing system with an optimized power efficiency.
Power efficiency and minimizing power usage are important issues in networked systems, such as communications systems and computing systems. Programs which monitor the usage of various components of a computer system and shut down or minimize some of those components have been used in the past.
However, one area in which such power conservation has not been utilized is with respect to processing units. Whether in networked computer systems or communications systems, optimizing the power efficiency of processing units has not been previously addressed. For example, computer systems with multiple processors operate all processors in parallel at the same time to improve overall system performance without consideration to the power usage involved.
In multiple processor systems, specific tasks such as disk operations, display operations and keyboard input may be assigned to each processor. Another method of improving performance is to assign specific programs, such as word processing and spreadsheet programs, to separate processors. What these systems fail to address is the power used when the processor units are idling. Even when idling, processors are using power with every tick of the processor clock. For high speed processors, this can result in a substantial power usage.
This problem is particularly evident in portable units where the power is limited to that which is available from batteries. One solution used in laptop computers is to slow the processor speed when the laptop computer is running on battery. For example, a processor chip may operate at 1 GHz when the computer is connected to an AC power outlet and at 500 MHz when running on the internal battery. This results in a significant impact on the performance of the system.
Likewise, communications systems such as cellular phones experience considerable idle time during which power continues to be used in order to keep the system ready to transmit or receive signals. This use of power even when idling causes portable, battery-powered units to require frequent recharging.
It is therefore an object of this invention to provide a networked processing system in which power usage is minimized.
It is a further object of this invention to provide a networked processing system in which performance is optimized.
It is a further object of this invention to provide a multi-tasking, multiple processor system in which the power efficiency is optimized.
It is a further object of this invention to provide a self-contained, miniaturized computer with a built in power source, flash memory, digital I/O interface and radio frequency (RF) transceiver for bi-directional communication.
The invention results from the realization that, in a multi-tasking, multi-processor environment, the power efficiency of the system can be optimized by coordinating the usage of processing units such that tasks are run on the appropriate speed processing unit and unused processing units are placed in sleep mode.
This invention features a networked computing system with improved power consumption comprising a plurality of processing units including at least first and second processing units. A coordinating protocol is operative on the first and second processing units and controls the operation of the system such that the power consumption of the system is minimized.
In a preferred embodiment, the first and second processing units are interconnected. The first processing unit operates at a first clock frequency, and the second processing unit operates at a second clock frequency. The first clock frequency may be lower than the second clock frequency.
The first processing unit assigns a task to the first or second processing units based on the clock frequency required to run the task such that the minimum power is used. The first processing unit may instruct the second processing unit to enter a minimum power usage mode. The first processing may activate the second processing unit from the minimum power usage mode when a task is to performed by the second processing unit. The first processing unit may transfer the coordinating protocol to the second processing unit.
The processing units may be communications device which may be bi-directional communications devices. The first processing unit may instruct the second processing unit to enter a minimum power usage mode for a preprogrammed time. The second processing unit may poll the first processing unit after the preprogrammed time. The preprogrammed time may be variable.
This inventions also provides a multiple processor computer system comprising a plurality of processing units, each of the plurality of processing units operating at a clock frequency. A first processing unit operates at a clock frequency lower than the remaining processing units. A coordinating protocol is operable on the first processing unit and coordinates the operation of the system such that the power efficiency is optimized.
In a preferred embodiment, each of the plurality of processing units operates at a different clock frequency. The first processing unit may transfer the coordinating protocol to a second processing unit of the plurality of processing units. The second processing unit may transfer the coordinating protocol to any of the plurality of processing units.
This invention also features a wireless communication system comprising a base unit and a plurality of terminal units in communication with the base unit. Each of the plurality of terminal units has a duty cycle. The base unit controls the duty cycle of each of the plurality of terminal units to optimize the power efficiency of the system.
In a preferred embodiment, the base unit may instruct at least one of the terminal units to enter a minimum power consumption mode for a preprogrammed time. The base unit and the plurality of terminal units may be bi-directional. The terminal unit may poll the base unit after the preprogrammed time.
This invention also features a method for optimizing the power efficiency of a multi-processor computer system including the steps of providing a plurality of processing units including at least first and second processing units, each processing unit operating at a clock frequency, and operating a coordinating protocol on the first processing unit. The coordinating protocol is operative to receive a request to perform a task, determine to which of the processing units to assign the task, and assign the task to one of the plurality of processing units. The coordinating protocol determines which processing unit to which a task is to be assigned based on optimizing the power efficiency of the system.
The method may also include the steps of transferring the coordinating protocol from the first processing unit to the second processing unit based on the speed required to run the coordinating protocol. The coordinating protocol may be further transferred from the second processing unit to any of the plurality of processing units based on the speed required to run the coordinating protocol.
This invention also features a self-contained, miniaturized computer system including first and second processing units, the first processing unit including a coordinating protocol operable to coordinate the operation of the first and second processing units, a power source, a flash memory module and a RF transceiver, wherein the coordinating protocol assigns tasks to the first and second processing units to optimize the power efficiency of the system.
In a preferred embodiment, the first processing unit operates at a clock frequency of 32 kHz and the second processing unit operates at a clock frequency of 4 MHz. The power source may be a battery.